74LS393 DATASHEET PDF

Nikozuru Recall that the 74LSs trigger on a falling edge, not a rising edge. I used datashete for the first stage to divide 60Hz to 10Hz. The pulse goes high then low, and the falling edge triggers the 74LS For this clock, I decided to go with the traditional 7-segment display to show the time. These versatile nixie tubes can allow for a variety of characters and digits with different styles.

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Nikozuru Recall that the 74LSs trigger on a falling edge, not a rising edge. I used datashete for the first stage to divide 60Hz to 10Hz. The pulse goes high then low, and the falling edge triggers the 74LS For this clock, I decided to go with the traditional 7-segment display to show the time.

These versatile nixie tubes can allow for a variety of characters and digits with different styles. This configuration helped solve the problem. I came to a point where I thought I had gotten the design, so I proceed to build the clock.

I figure since the latter was normally used in older computer systems, the power supply and input signals are expected to be well-filtered and free of noise. One advantage to use what is essentially a binary clock with 7-segment decoders is to have small neon bulbs or LEDs driven directly from the BCD outputs. Without the K resistor and 0. However, after trying the chip out with two nixies, I found that the brightness was not very strong. I personally prefer hour mode.

I was faced with the problem of the clock starting at 00 hours, but the clock does count nicely to 12 and resets back to The 74LS clock input triggers on a falling-edge of a square wave when the square wave signal drops from a logic 1 to 0. I built a case out of cedar, and the amount of space I had inside the case was rather limited so I was unable to pursue my idea of using neon bulbs or LEDs for displaying the binary time directly from the 74LS counters.

Most chips come with four AND gates in one, or 6 inverters in one. It took some experimentation before I could get the signals to work correctly between the chips. I figured that with the in the front, it would buffer out more of the noise and generate a cleaner clock pulse for the 74LS chips. I experimented with using 74LS dual binary counter chips. So, when the hours runs to 13, the AND gate will reset the hours to zero, then the DRL will produce a logic 1 because it senses 00 hours.

I had to use a very small 8-volt transformer that just barely fits inside the case to supply the low voltage power. I originally planned on using a Mostek MK 6-digit clock chip that multiplexes the digits. After overcoming the noise problem with the 74LSs in the clock, I learned of another minor design issue. This current draw will pull up the clock input of the 74LS to a logic 1 momentarily. Anyway, on to the pictures. I never had a problem with this in my other two clocks that run off mains, and I discovered the reason after taking a closer look at the datasheets.

However, I had to delay the pulse from the DRL until the 10 minutes counter finished sending its clock pulse to the 1 hours counter.

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